The present invention relates to testing signal integrity, and more particularly to pattern identification and bit level measurements on repetitive patterns.
For testing signal integrity of certain high speed serial digital signals, such as Serial ATA-II signals defined by an electrical specification (Version 1.0 dated May 19, 2004), differential voltage measurements are specified. The measurements need to be on a signal that has a pre-defined repetitive pattern. The specification generally specifies a methodology that implies the use of a high bandwidth oscilloscope in a waveform database (wfmDB) mode to perform this measurement. The wfmDB mode is the acquisition process of sampling an analog input signal after a trigger event, digitizing each sample of the analog input signal to convert it to digital data, assembling the digital data into a waveform memory, and displaying a waveform that is the accumulation of several acquisitions. The waveform displays not only time and amplitude, but also a count of the number of times a specific sample has been acquired over multiple acquisitions. The value at each point (time after trigger event and amplitude) on the waveform is a counter that reflects such hit intensity. However this specified methodology has some limitations, as indicated below.                A pattern trigger is needed to accumulate samples in the wfmDB mode so that the acquired signal has the same pattern. However with the pattern trigger decoding, start and stop of the incoming data is not possible so there is a chance of false triggering, which leads to an incorrect “eye” pattern as shown in FIG. 1.        Further the trigger bandwidth of the oscilloscope is limited, for example to 1.25 Gbps, and therefore cannot be used for high bandwidth signals, such as the Serial ATA signal having a bandwidth of 1.5 Gbps and 3 Gbps.        Finally the wfmDB mode is limited to a defined data matrix resolution, such as 500×200. For a 3 Gbps signal a unit interval (one clock cycle) is 333.333 ps so the acquisition for a 20-bit pattern is approximately 7 ns. The horizontal resolution of the data matrix is approximatelyl 3 ps. The specification, such as the Serial ATA specification, specifies a region of each bit within which the measurement should be taken, i.e., between 45% and 55% of each bit—the middle of the bit. Thus the number of pixels available in the period 33.3 ps (45% and 55% of a bit) is two, which is not good enough to ascertain the correct voltage level.        
What is desired is a better technique for performing pattern identification and bit level measurements on a signal containing repetitive patterns arriving at sporadic time intervals.